1. Field of the Invention
The present invention relates to a potential relationship in an erasing operation of a nonvolatile semiconductor memory.
2. Description of the Related Art
A nonvolatile semiconductor memory, such as a NAND type flash memory, in which data of two levels or more is stored by a charge amount in a charge storage layer, has three basic operations of programming, reading, and erasing. The programming means an operation for injecting electrons into the charge storage layer, and the erasing means an operation for emitting electrons from the charge storage layer or injecting holes into the charge storage layer.
In the nonvolatile semiconductor memory, a memory cell array includes memory blocks (for example, NAND blocks), and units of memory block is erased at one time (for example, see Jpn. Pat. Appln. KOKAI Publication Nos. 2-196469 and 2007-281267).
During data erasing, in the selected memory block, channel portions of all the memory cells are set to an erasing potential (high positive potential) and all word lines (control gate electrodes of memory cells) are set to a ground potential.
Accordingly, in all the memory cells of the selected memory block, electrons are emitted from the charge storage layer to the channel portion, or holes are injected from the channel portion into the charge storage layer, thereby performing the data erasing.
In the non-selected memory block, potentials at all the word lines are boosted to a boost potential (a positive high potential lower than the erasing potential) by capacitive coupling, because all the word lines are set to floating while the channel portions of all the memory cells are set to the erasing potential.
Accordingly, the data stored in any memory cells of the non-selected memory block is not erased.
Transfer transistor blocks are provided according to the memory blocks. Each transfer transistor block includes high-potential transfer N-channel MOS transistors having the same number as the word lines in one block. In the high-potential transfer N-channel MOS transistors, one end of a diffusion layer is connected to word lines in one block, and the other end of the diffusion layer is connected to potential transfer lines (control gate lines). And one of the high-potential transfer N-channel MOS transistors in each of the transfer transistor blocks have the potential transfer lines in common.
During the erasing, the ground potential is applied to the potential transfer line, the high-potential transfer N-channel MOS transistor in the transfer transistor block corresponding to the selected memory block is turned on, and the high-potential transfer N-channel MOS transistor in the transfer transistor block corresponding to the non-selected memory block is turned off.
Therefore, in the high-potential transfer N-channel MOS transistor in the transfer transistor block corresponding to the non-selected memory block, the ground potential is applied to a source (potential transfer line side), and the boost potential is applied to a drain (word line side).
At this state, a minutely small amount of punch-through leakage is produced between the source diffusion layer and the drain diffusion layer in the high-potential transfer N-channel MOS transistor in the transfer transistor block corresponding to the non-selected memory block, which causes electrons to be trapped in a gate insulating film of the high-potential transfer N-channel MOS transistor or in an interface between the semiconductor substrate and the source/drain diffusion layer.
Accordingly, when the number of erasing times is increased to apply a voltage stress for a long time between the source diffusion layer and the drain diffusion layer of the high-potential transfer N-channel MOS transistor in a cut-off state, the number of trapped electrons is increased to degrade reliability, such as reduction of high-potential transfer characteristics and programming/erasing error.